This invention relates to a circuit which combines a desaturation detector and a breakdown voltage clamp for use with power transistors.
Desaturation detection circuits with fast response times and precise detection thresholds are desirable for systems employing power transistors to protect the power transistors from excess current, for example, from a load short circuit. During the initial turn on of a power transistor, however, desaturation detection circuitry must be disabled for a time sufficient to allow the transistor to reach saturation. In the past, this problem has been solved by using detection circuits with response times greater than the time it takes for the power transistor to initially reach saturation. Unfortunately, such slow response times often provide inadequate protection during normal operation. In addition to being too slow, previous desaturation detection circuits often had imprecise detection thresholds due to system component tolerances. This had the effect of further undermining reliable sensing of desaturation events.
Another problem facing power systems is the occurrence of overvoltages across the power transistors. Previous solutions to the overvoltage problem have employed snubber circuits. While snubber circuits have been shown to provide adequate protection against overvoltage conditions, they require the use of high quality, high voltage capacitors which are bulky and expensive.
Thus, there is a need for a desaturation detection circuit with a fast response time and a precise detection threshold. There is also a need for overvoltage clamp protection which eliminates the need for snubber circuits.